01 | Disable cache, enable ROM, high speed on, turn off cache's, disable EISA NMI's, set master/slave IRQ's to edge triggered, disable reset chaining; Disable 82C601 chip |
05 | Initialize address decoder, 640K RAM; Set BIOS as cacheable, enable extended memory |
06 | Clear shutdown flag |
07 | 8042 keyboard controller test; Wait till 8042 buffer empty; Disable 8042 command, read 8042 output buffer; Set response ok to DMA page register channel 2 |
08 | Send 8042 keyboard controller NOP command; Get 8042 self test result; Send DMA page register channel 2; If xx=55, then self test ok |
09 | Test BIOS ROM checksum |
0A | Read CMOS registers 3 times to clear pending CMOS real time clock interrupts; Disable real time clock interrupts; Check battery |
0B | Bad CMOS RAM battery |
0C | Send command to port 61 to disable parity and speaker |
0D | Test 8254programmable interrupt timer counter |
0E | One of the counter timers is bad; xx indicates the bad counter |
0F | Enable and check memory refresh |
10 | Memory refresh failed |
11 | Check and clear the first 64K RAM in real mode; Disable NMI; Clear parity latches; Fill 64K with 5555 and check it, then AAA and check it, then 0000 |
12 | First 64K RAM memory test failed |
13 | First 64K RAM memory test passed |
14 | Reset the warm boot flag and test CMOS RAM; Turn off caches; Shadow the BIOS; set high speed; Calculate high speed and initialize GP flag; Set low speed and turn off cache if CMOS not good or CMOS speed not high |
16 | Check shutdown flag 123x |
17 | Reset was cold boot |
18 | Prepare 8259 programmable interrupt controllers |
19 | 8259 programmable interrupt controllers initialization failed; Initialize video and display the error message |
1A | Test 8259 programmable interrupt controller |
1B | Set interrupt 0F to unexpected interrupt vector; Enable timer and interrupt |
1C | Set interrupt 08 to timer 0 interrupt vector |
1D | Timer interrupt did not occur; Initialize video and display error message |
1E | Initialize interrupt vectors |
1F | Initialize interrupt vectors 00-6F to temporary interrupt service routines |
20 | Set vectors for interrupt 02-1F |
21 | Set interrupt vectors for 70-77, clear vectors 60-67 and 78-FF |
22 | Clear interrupt vectors for 41 and 46 |
23 | Read 8042 keyboard controller self test results from DMA page register channel 2 |
24 | Test for proper 8042 keyboard controller self test result |
25 | 8042 keyboard controller self test failed |
26 | Initialize 8042 keyboard controller |
27 | Check shutdown flag=123x; If no=cold boot |
28 | If cold boot or CMOS RAM is bad, then install video ROM and initialize video; Initialize equipment flags according to primary video adapter and CMOS RAM content; Initialize POST status |
29 | If not cold boot and CMOS RAM ok; Install video ROM and initialize video for mono/CGA; Initialize equipment flags according to primary video adapter and CMOS RAM contents |
2A | Check for bad CMOS RAM |
2B | Check shutdown flag=123x |
2C | If cold boot; Turn off caches; Test memory for size and reinitialize cache status |
2D | Turn off "POST fail" CMOS RAM bit and display and error messages; Initialize keyboard RAM |
2E | Initialize 8042 keyboard controller and test keyboard |
2F | Initialize time of day in real time clock |
30 | Test for and install floppy drive controller |
31 | Enable 82C601 IDE interface; Test for and install hard disk |
32 | Test 8259 programmable interrupt controller DMA registers with 55 then AA, then initialize them to 00 |
33 | Test for and initialize math coprocessor |
34 | Test for and initialize parallel and serial ports |
35 | Initialize RAM variables for bad CMOS time, date, checksum and battery |
36 | Wait for user to press Esc or Space; Check for keyboard lock; Clear keyboard lock override; Beep to indicate speed; Display error messages |
37 | Enable system clock tick (IRQ 0); Enable keyboard (IRQ 1); Enable slave interrupt controller (IRQ 2) |
38 | Initialize RAM variables for Ctrl-Alt_Esc |
39 | Enter setup is keystroke pressed |
3A | Clear screen and update equipment flags according to CMOS RAM contents; Shadow ROM's; Enable/disable cache through CMOS RAM |
3B | Initialize floppy and hard drives |
3C | Set POST failed bit in CMOS RAM; Scan for and initialize adapter ROM's |
3D | Clear the shutdown flag to 0; Disable gate A20 and enable memory wrap in real mode |
3E | Set vectors for interrupts 3B-3F; Clear post fail bit in CMOS RAM |
3F | Call interrupt 19 boot loader |